The disclosure generally relates to a half-rate clock data recovery circuit and, more particularly, to a half-rate clock data recovery circuit capable of dynamically adjusting signal delay of the sampling signal.
A voltage-controlled oscillator is typically employed in the conventional half-rate clock data recovery circuit to generate an in phase clock signal and a quadrature phase clock signal having 90 degrees phase difference with the in phase clock signal. In the conventional half-rate clock data recovery circuit, the in phase clock signal is utilized by a data sampling circuit as a data sampling clock of an input data, and the quadrature phase clock signal is utilized by an edge sampling circuit as an edge sampling clock of the input data. In theory, when the rising edge of the quadrature phase clock signal is aligned with the edge of the eye diagram of the input data, the rising edge of the in phase clock signal should be aligned with the central portion of the eye diagram of the input data. In this situation, the bit error rate of the half-rate clock data recovery circuit can be reduced by adopting the in phase clock signal to be the data sampling clock of the input data.
In the realistic environment, however, the eye diagram of the input data is often not an ideal symmetric eye due to the non-linear characteristic of the eye recovery circuit. Additionally, the hold time issue typically occurs in the conventional edge sampling circuit. Accordingly, utilizing the in phase clock signal and the quadrature phase clock signal that having 90 degrees phase difference with each other as sampling clocks often causes the sampling point of the input data to deviate from the best sampling point of the eye diagram when the loop is locked, thereby increasing the bit error rate of the half-rate clock data recovery circuit.